1. Field of the Invention
The present invention relates generally to data drivers and, more particularly, to data drivers for signal conditioning systems.
2. Description of the Related Art
Conventional complementary metal-oxide semiconductor (CMOS) logic circuits facilitate single-ended transmission of data. For example, a basic building block of CMOS logic is a CMOS inverter which includes first and second CMOS transistors that are serially-coupled between first and second voltage rails (e.g., between VDD and ground). When the gates of the first and second transistors are successively coupled to the first and second rail voltages, the inverter output successively provides second and first rail voltages as output signals. Among its other advantages, CMOS logic uses substantially less power than many other systems (e.g., transistor-transistor logic (TTL) and emitter-coupled logic (ECL)). In addition, MOS logic circuits can directly drive TTL circuits.
Low voltage differential signaling (LVDS) is a data signaling technology that provides differential current signals for high-rate data transmission. Because noise is generally equally coupled onto differential signal paths, it is substantially rejected by a remote receiver which differentially receives the LVDS signals. Accordingly, LVDS differential transmission is less susceptible to common-mode noise than single-ended transmission systems. Because LVDS drivers generate low-level differential current signals, their power consumption is reduced from conventional single-ended transmission systems and is almost flat regardless of the data rate.
LVDS technology is currently standardized in the ANSI/TIA/EIA-644 Standard of the Telecommunications Industry Association/Electronics Industries Association (TIA/EIA) and in the IEEE 1596.3 Standard of the Institute for Electrical and Electronics Engineering (IEEE).
Because of their different needs, some potential users of signal conditioning circuits (e.g., analog-to-digital converters (ADCs)) prefer output signals that are compatible with CMOS/TTL circuits and others prefer output signals that are compatible with LVDS circuits. In order to enhance their attractiveness to a large number of customers, signal conditioning circuits are, therefore, preferably configured to provide both CMOS and LVDS drive signals.
However, current ADCs often provide a large number of digital bits (e.g., on the order of 16) and are generally fabricated as integrated circuits with limited package dimensions (e.g., on the order of 15 millimeters). Accordingly, it has become increasingly difficult to provide the large number of integrated-circuit pins that are required to provide both CMOS and LVDS drive signals.
The present invention is directed to data driver systems that have programmable modes of operation to thereby facilitate selection of output signal forms and reduction of output ports.
In an exemplary embodiment, rail-to-rail and LVDS drivers share output ports and are combined with a multiplexer that selectively configures them in driver and high output-impedance states.
The novel features of the invention are set forth with particularity in the appended claims. The invention will be best understood from the following description when read in conjunction with the accompanying drawings.